FIGS. 9 and 10 show a block diagram and a circuit construction diagram of a conventional digital transmission circuit using source coupled field effect transistors. In these figures, reference numeral 1 designates a differential amplifier comprising field effect transistors (hereinafter referred to as FET) Q.sub.1 and Q.sub.2, constituting source coupled switches, loads Z.sub.1 and Z.sub.2 of the FETs Q.sub.1 and Q.sub.2, and an FET Q.sub.3 as a constant current load which connects the source terminal to the power supply terminal. Reference character V.sub.ss designates a power supply terminal of the digital transmission circuit. The other power supply terminal of the circuit is grounded.
A description is given of the operation.
Generally, suppose that the drain current of the FET is I.sub.DS, drain voltage V.sub.D, gate voltage V.sub.G, source voltage V.sub.S, and the threshold voltage of the gate V.sub.TH, the static characteristics of the FET are: saturation region: I.sub.DS =K(V.sub.G -V.sub.s -V.sub.TH).sup.2
: 0&lt;V.sub.G -V.sub.S -V.sub.TH .ltoreq.V.sub.D -V.sub.S
non-saturation region: I.sub.DS =K{2(V.sub.G -V.sub.S -V.sub.TH).multidot.(V.sub.D -V.sub.S) -(V.sub.D -V.sub.S).sup.2}
: V.sub.D -V.sub.S &lt;V.sub.G -V.sub.S -V.sub.TH
switch off region: I.sub.DS =0
: V.sub.G -V.sub.S -V.sub.TH .ltoreq.0
Here, reference character K is transconductance
In FIG. 10, it is assumed that all FETs are operated in the saturation region.
First of all, the DC characteristics of the digital transmission circuit will be described In FIG. 10, suppose that DC voltages V.sub.IN and V.sub.IN are input to the gate terminals IN and IN of the source coupled FETs Q.sub.1 and Q.sub.2, respectively. Then, supposed that the drain current of the FETs Q.sub.1 and Q.sub.2 are I.sub.1 and I.sub.2 and the current flowing through the constant current load FET Q.sub.3 is I.sub.0.
In the above-described digital transmission circuit, when the characteristics of the FETs Q.sub.1 Q.sub.2 and the loads Z.sub.1, Z.sub.2 are equal to each other, respectively, the output voltages V.sub.OUT and V.sub.OUT taken out from the drain terminals OUT and OUT of the respective FETs Q.sub.1 and Q.sub.2 are, supposing that the loads of the FETs Q.sub.1 and Q.sub.2 are Z.sub.1 =Z.sub.2 =Z: EQU I.sub.0 =I.sub.1 +I.sub.2 EQU V.sub.OUT =-Z.multidot.I.sub.1 EQU V.sub.OUT =-Z.multidot.I.sub.2
Therefore, the voltage characteristics are as shown in FIG. 11. That is, when a constant voltage is applied to the terminal IN, the voltage gain [V.sub.OUT /(V.sub.IN -V.sub.IN)] has an inclination of G.sub.0 and the output voltage is represented by EQU V.sub.OUT =G.sub.0 .multidot.(V.sub.IN -V.sub.IN)-Z.multidot.I.sub.0 /2 (1)
Next, a description is given of the pulse response of the above-described digital transmission circuit.
Suppose that a constant voltage V.sub.R is input to the terminal IN and a pulse signal F.sub.IN (t) having a mark density of 1/2 as shown in FIG. 12(a) is input to the terminal IN. Further, suppose that the input/output of the signal is performed in the linear region (a region where the input signal is linearly amplified) of the I/0 characteristics of FIG. 11. Then, when the output signal at the output OUT is made F.sub.OUT (t) and there is no frequency dependency in the voltage gain of the circuit, this F.sub.OUT (t) is represented by the following formula from the above-described formula (1), EQU F.sub.OUT (t)=G.sub.0 .multidot.(F.sub.IN (t)-V.sub.R)-Z.multidot.I.sub.0 /2.
When a GaAs MESFET is used, however, the transconductance gm or drain conductance Gd, which are device parameters of an FET, are frequency dependent at low frequency (below 100 kHz) and influence the circuit characteristics. The gain of the circuit has a frequency dependency and is gradually reduced from DC toward higher frequencies as shown in FIG. 13. In digital transmission, the input signal is a pulse signal whose mark density always changes and the pulse waveform includes a DC component dependent on the mark density and a high frequency component. Since the gain varies for the respective components because of the above-described frequency dependency, the DC level varies significantly with the amplitude of the high frequency component and there is a change in the output level (H level and L level) therewith.
With respect to the above-described phenomenon, the outputs when pulses having different mark densities are input are compared.
A case where a signal F.sub.IN(1/2) (t) which has a mark density of 1/2 as shown in FIG. 12(a) is input and a case where a signal F.sub.IN(1/8) (t) which has mark density of 1/8 as shown in FIG. 12(b) is input are considered.
When the pulse of FIGS. 12(a) and 12(b) are divided into the DC component and high frequency component, the followings are obtained. EQU F.sub.IN(1/2) (t)=a.sub.0 +a.sub.1 ( 2) EQU F.sub.IN(1/8) (t)=c.sub.0 +c.sub.1 ( 3)
Here, ##EQU1##
Now, when the DC voltage gain is G.sub.0, the voltage gain above 100 kHz is G.sub.1, and 1/T&gt;&gt;100 kHz, the output signal F.sub.OUT is represented as in the following for signals of respective mark densities; EQU F.sub.OUT(1/2) (t)=-G.sub.0 .multidot.V.sub.R -Z.multidot.I.sub.0 /2+(G.sub.0 -G.sub.1).multidot.a.sub.o +G.sub.1 .multidot.F.sub.IN(1/2) (t) (4) EQU F.sub.OUT(1/8) (t)=-G.sub.0 .multidot.V.sub.R -Z.multidot.I.sub.0 /2+(G.sub.0 -G.sub.1).multidot.c.sub.0 +G.sub.1 .multidot.F.sub.IN(1/8) (t) (5)
the output waveforms are shown in FIG. 14(a) and 14(b).
The signal level difference represented by the formulae (4) and (5) (formula(4)-formula(5)) becomes EQU F.sub.OUT(1/2) (t)-F.sub.OUT(1/8) (t)=(G.sub.0 -G.sub.1)(a.sub.0 -c.sub.0)+G.sub.1 .multidot.{F.sub.in(1/2) (t)-F.sub.in(1/8) (t)} . . . (6)
In the above-described formula (6), the second term does not vary the output level (H level and L level). Therefore, in the signals having mark densities of 1/2 and 1/8, the variation of output level (H level and L level) arises from .DELTA.DC.sub.(1/2-1/8) =(G.sub.0 -G.sub.1)(a.sub.0 -c.sub.0), that is, by the amount of (voltage gain at DC-voltage gain at high frequency).multidot.(DC level difference of the input signal).
The conventional digital transmission circuit is constructed as described above and there is a frequency dependency as shown in FIG. 13 in the circuit gain because of variation of the device parameter of GaAs MESFETs with frequency, and therefore the output level varies with the duty cycle of input signal.